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DS1202, DS1202S
DS1202, DS1202S Serial Timekeeping Chip
FEATURES
PIN ASSIGNMENT
NC X1 X2 GND 1 2 3 4 8 7 6 5 VCC SCLK I/O RST
* Real time clock counts seconds, minutes, hours, date
of the month, month, day of the week, and year with leap year compensation valid up to 2100
* 24 x 8 RAM for scratchpad data storage * Serial I/O for minimum pin count * 2.0-5.5 volt full operation * Uses less than 300 nA at 2 volts * Single-byte or multiple-byte (burst mode) data transfer for read or write of clock or RAM data
8-PIN DIP NC X1 X2 GND 1 2 3 4 8 7 6 5 VCC SCLK I/O RST
8-PIN SOIC (208 mil) NC NC X1 NC X2 NC NC 1 2 3 4 5 6 7 8 16-PIN SOIC 16 15 14 13 12 11 10 9 VCC NC SCLK NC I/O NC NC RST
* 8-pin DIP or optional 16-pin SOIC for surface mount * Simple 3-wire interface * TTL-compatible (VCC = 5V) * Optional industrial temperature range -40C to +85C
(IND)
ORDERING INFORMATION
DS1202 DS1202S DS1202S-8 DS1202N DS1202SN DS1202SN-8 8-pin DIP 16-pin SOIC 8-pin SOIC 8-pin DIP (IND) 16-pin SOIC (IND) 8-pin SOIC (IND)
GND
PIN DESCRIPTION
NC X1, X2 GND RST I/O SCLK VCC - - - - - - - No Connection 32.768 KHz Crystal Input Ground Reset Data Input/Output Serial Clock Power Supply Pin
DESCRIPTION
The DS1202 Serial Timekeeping Chip contains a real time clock/calendar and 24 bytes of static RAM. It communicates with a microprocessor via a simple serial interface. The real time clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with less than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. Interfacing the DS1202 with a microprocessor is simplified by using synchronous serial communication. Only three wires are required to communicate with the clock/RAM: (1) RST (Reset), (2) I/O (Data line), and (3) SCLK (Serial clock). Data can be transferred to and from the clock/ RAM one byte at a time or in a burst of up to 24 bytes. The DS1202 is designed to operate on very low power and retain data and clock information on less than 1 microwatt.
ECopyright 1997 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books.
032697 1/11
DS1202, DS1202S
OPERATION
The main elements of the Serial Timekeeper are shown in Figure 1: shift register, control logic, oscillator, real time clock, and RAM. To initiate any transfer of data, RST is taken high and eight bits are loaded into the shift register providing both address and command information. Data is serially input on the rising edge of the SCLK. The first eight bits specify which of 32 bytes will be accessed, whether a read or write cycle will take place, and whether a byte or burst mode transfer is to occur. After the first eight clock cycles have occurred which load the command word into the shift register, additional clocks will output data for a read or input data for a write.
The number of clock pulses equals eight plus eight for byte mode or eight plus up to 192 for burst mode.
COMMAND BYTE
The command byte is shown in Figure 2. Each data transfer is initiated by a command byte. The MSB (Bit 7) must be a logic 1. If it is zero, further action will be terminated. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1. Bits one through five specify the designated registers to be input or output, and the LSB (Bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic 1. The command byte is always input starting with the LSB (bit 0).
DS1202 BLOCK DIAGRAM Figure 1
32.768 KHz
X1 I/O REAL TIME CLOCK OSCILLATOR AND DIVIDER
X2
INPUT SHIFT REGISTERS
DATA BUS
SCLK
RST
COMMAND AND CONTROL LOGIC
ADDRESS BUS
24 X 8 RAM
ADDRESS/COMMAND BYTE Figure 2
7 1 6 RAM CK 5 A4 4 A3 3 A2 2 A1 1 A0 0 RD W
032697 2/11
DS1202, DS1202S
RESET AND CLOCK CONTROL
All data transfers are initiated by driving the RST input high. The RST input serves two functions. First, RST turns on the control logic which allows access to the shift register for the address/command sequence. Second, the RST signal provides a method of terminating either single byte or multiple byte data transfer. A clock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, data must be valid during the rising edge of the clock and data bits are output on t he falling edge of clock. All data transfer terminates if the RST input is low and the I/O pin goes to a high impedance state. Data transfer is illustrated in Figure 3.
Each byte that is written to will be transferred to RAM regardless of whether all 24 bytes are written or not.
CLOCK/CALENDAR
The clock/calendar is contained in eight write/read registers as shown in Figure 4. Data contained in the clock/ calendar registers is in binary coded decimal format (BCD).
CLOCK HALT FLAG
Bit 7 of the seconds register is defined as the clock halt flag. When this bit is set to logic 1, the clock oscillator is stopped and the DS1202 is placed into a low-power standby mode with a current drain of not more than 100 nanoamps. When this bit is written to logic 0, the clock will start.
DATA INPUT
Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the next eight SCLK cycles. Additional SCLK cycles are ignored should they inadvertently occur. Data is input starting with bit 0. Due to the inherent nature of the logic state machine, writing times containing an absolute value of "59" seconds should be avoided.
AM-PM/12-24 MODE
Bit 7 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10 hour bit (20-23 hours).
DATA OUTPUT
Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written. Additional SCLK cycles retransmit the data bytes should they inadvertently occur so long as RST remains high. This operation permits continuous burst mode read capability. Data is output starting with bit 0.
WRITE PROTECT BIT
Bit 7 of the control register is the write protect bit. The first seven bits (bits 0-6) are forced to zero and will always read a zero when read. Before any write operation to the clock or RAM, bit 7 must be zero. When high, the write protect bit prevents a write operation to any other register.
BURST MODE
Burst mode may be specified for either the clock/calendar or the RAM registers by addressing location 31 decimal (address/command bits one through five = logical one). As before, bit six specified clock or RAM and bit 0 specifies read or write. There is no data storage capacity at locations 8 through 31 in the Clock/Calendar Registers or locations 24 through 31 in the RAM registers. When writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred. However, when writing to RAM in burst mode it is not necessary to write all 24 bytes for the data to transfer.
CLOCK/CALENDAR BURST MODE
The clock/calendar command byte specifies burst mode operation. In this mode the eight clock/calendar registers can be consecutively read or written (see Figure 4) starting with bit 0 of address 0.
RAM
The static RAM is 24 x 8 bytes addressed consecutively in the RAM address space.
RAM BURST MODE
The RAM command byte specifies burst mode operation. In this mode, the 24 RAM registers can be consecutively read or written (see Figure 4) starting with bit 0 of address 0.
032697 3/11
DS1202, DS1202S
REGISTER SUMMARY
A register data format summary is shown in Figure 4.
CRYSTAL SELECTION
A 32.768 KHz crystal, can be directly connected to the DS1202 via pins 2 and 3 (X1, X2). The crystal selected for use should have a specified load capacitance (CL) of 6 pF. The crystal is connected directly to the X1 and X2
pins. There is no need for external capacitors or resistors. Note: X1 and X2 are very high impedance nodes. It is recommended that they and the crystal be guard- ringed with ground and that high frequency signals be kept away from the crystal area. For more information on crystal selection and crystal layout considerations, please consult Application Note 58, "Crystal Considerations with Dallas Real Time Clocks".
DATA TRANSFER SUMMARY Figure 3
SINGLE BYTE TRANSFER
SCLK
RST 0 I/O R/W 1 A0 2 A1 3 A2 4 A3 5 A4 6 R/C 7 1 DATA INPUT/OUTPUT 0 1 2 3 4 5 6 7
ADDRESS COMMAND
BURST MODE TRANSFER
SCLK
RST 0 I/O R/W 1 1 2 1 3 1 4 1 5 1 6 R/C 7 1 DATA I/O BYTE 1 DATA I/O BYTE N 0 1 2 4 5 6 7
ADDRESS COMMAND
FUNCTION CLOCK RAM
BYTE N 8 24
SCLK n 72 200
032697 4/11
DS1202, DS1202S
REGISTER ADDRESS/DEFINITION Figure 4
REGISTER ADDRESS A. CLOCK
7 SEC 1 6 0 5 0 4 0 3 0 2 0 1 0 0 RD W 00-59 CH 10 SEC SEC
REGISTER DEFINITION
MIN
1
0
0
0
0
0
1
RD W
00-59
0
10 MIN
MIN
HR
1
0
0
0
0
1
0
RD W
01-12 00-23
12/ 24
0
10 A/P
HR
HR
DATE
1
0
0
0
0
1
1
RD W
01-28/29 01-30 01-31
0
0
10 DATE
DATE
MONTH
1
0
0
0
1
0
0
RD W
01-12
0
0
0
10 M
MONTH
DAY
1
0
0
0
1
0
1
RD W
01-07
0
0
0
0
0
DAY
YEAR
1
0
0
0
1
1
0
RD W
0-99
10 YEAR
YEAR
CONTROL
1
0
0
0
1
1
1
RD W
WP
FORCED TO ZERO
CLOCK BURST
1
0
1
1
1
1
1
RD W
B. RAM
RAM 0 1 1 0 0 0 0 0 RD W RAM DATA 0
RAM 23
1
1
1
0
1
1
1
RD W
RAM DATA 23
RAM BURST
1
1
1
1
1
1
1
RD W
032697 5/11
DS1202, DS1202S
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.3V to +7.0V 0C to 70C -55C to +125C 260C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Supply Voltage Logic 1 Input Logic 0 Input SYMBOL VCC VIH VIL VCC=2.0V VCC=5V MIN 2.0 2.0 -0.3 -0.3 TYP MAX 5.5 VCC+0.3 +0.3 V +0.8 V V
(0C to 70C)
UNITS NOTES 1 1 1
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage I/O Leakage Logic 1 Output ILI ILO VOH VCC=2V VCC=5V VCC=2V VCC=5V VCC=2V VCC=5V VCC=2V VCC=5V VCC=2V VCC=5V 1.6 SYMBOL MIN
(0C to 70C; VCC = 2.0 to 5.5V*)
TYP MAX +500 +500 UNITS A A V 2.4 0.4 V 0.4 0.4 mA 1.2 0.3 1 100 nA 100 10 A 4 5 3 NOTES 6 6 2
Logic 0 Output
VOL
Active Supply Current
ICC
Timekeeping Current
ICC1
Leakage Current *Unless otherwise noted.
ICC2
CAPACITANCE
PARAMETER Input Capacitance I/O Capacitance Crystal Capacitance SYMBOL CI CI/O CX CONDITION TYP 5 10 6 MAX UNITS pF pF pF
(tA = 25C)
NOTES
032697 6/11
DS1202, DS1202S
AC ELECTRICAL CHARACTERISTICS
PARAMETER Data to CLK Setup SYMBOL tDC VCC =2V VCC=5V VCC=2V VCC=5V VCC=2V VCC=5V VCC=2V VCC=5V VCC=2V VCC=5V VCC=2V VCC=5V VCC=2V VCC=5V VCC=2V VCC=5V VCC=2V VCC=5V VCC=2V VCC=5V VCC=2V VCC=5V 4 1 1000 DC 1000 MIN 200
(0C to 70C; VCC = 2.0 to 5.5V*)
TYP MAX UNITS ns 50 280 ns 70 800 ns 200 ns 250 1000 ns 250 0.5 MHz 2.0 2000 ns 500 s 7 7, 7 12 7, 7 12 7 7 8, 9 7, 8 7 NOTES 7
CLK to Data Hold
tCDH
CLK to Data Delay
tCDD
CLK Low Time
tCL
CLK High Time
tCH
CLK Frequency
fCLK
CLK Rise and Fall
tR, tF
RST to CLK Setup
tCC
CLK to RST Hold
tCCH
ns 250 4 1 280 ns 70 s
7
RST Inactive Time
tCWH
7
RST to I/O High Z *Unless otherwise noted.
tCDZ
7
032697 7/11
DS1202, DS1202S
TIMING DIAGRAM: READ DATA TRANSFER Figure 5
RESET tCC
CLOCK tCDH tDC DATA INPUT/ OUTPUT 0 1 7 tCDD tCDZ
COMMAND BYTE
TIMING DIAGRAM: WRITE DATA TRANSFER Figure 6
tCWH RESET tCC tCL CLOCK tCDH tDC DATA INPUT/ OUTPUT 0 1 7 tCH tR tF tCCH
COMMAND BYTE
NOTES:
1. All voltages are referenced to ground. 2. Logic one voltages are specified at a source current of 1 mA at VCC=5V and 0.4 mA at VCC=2V, VOH=VCC for capacitive loads. 3. Logic zero voltages are specified at a sink current of 4 mA at VCC=5V and 1.5 mA at VCC=2V. 4. ICC1 is specified with I/O open, RST set to a logic 0, and clock halt flag=0 (oscillator enabled). 5. ICC is specified with the I/O pin open, RST high, SCLK=2 MHz at VCC=5V; SCLK=500 KHz, VCC=2V and clock halt flag=0 (oscillator enabled). 6. RST, SCLK, and I/O all have 40K pull-down resistors to ground. 7. Measured at VIH=2.0V or VIL=0.8V and 10 ms maximum rise and fall time. 8. Measured at VOH=2.4V or VOL=0.4V. 9. Load capacitance = 50 pF.
032697 8/11
DS1202, DS1202S
10. ICC2 is specified with RST, I/O, and SCLK open. The clock halt flag must be set to logic one (oscillator disabled). 11. At power-up, RST must be at a logic 0 until VCCy2 volts. Also, SCLK must be at a logic 0 when RST is driven to a logic one state. 12. If tCH exceeds 100 ms with RST in a logic one state, then ICC may briefly exceed ICC specification.
DS1202 SERIAL TIMEKEEPER 8-PIN DIP
8 5 PKG DIM B A IN. MM B IN. MM 1 A 4 C IN. MM D IN. MM E IN. MM C F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM D 8-PIN MIN 0.360 0.240 0.120 0.300 0.015 0.110 0.090 0.320 0.008 0.015 MAX 0.400 0.260 0.140 0.325 0.040 0.140 0.110 0.370 0.012 0.021
F K G E
J
H
032697 9/11
DS1202, DS1202S
DS1202S SERIAL TIMEKEEPER 16-PIN SOIC
K G
F B H phi
J
L
PKG 1 DIM A IN. MM C B IN. MM C IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM L IN MM phi
16-PIN MIN 0.500 12.70 0.290 7.37 0.089 2.26 0.004 0.102 0.094 2.38 MAX 0.511 12.99 0.300 7.65 0.095 2.41 0.012 0.30 0.105 2.68
A
E
0.050 BSC 1.27 BSC 0.398 10.11 0.009 0.229 0.013 0.33 0.016 0.406 0 0.416 10.57 0.013 0.33 0.019 0.48 0.040 1.20 8
032697 10/11
DS1202, DS1202S
DS1202S8 8-PIN SOIC 200 MIL
K G
J B H 0-8 deg. typ. 1 L
F
PKG DIM C A A IN. MM B IN. MM C IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM L IN. MM
8-PIN MIN 0.203 5.16 0.203 5.16 0.070 1.78 0.004 0.102 0.074 1.88 0.050 BSC 1.27 BSC 0.302 7.67 0.006 0.152 0.013 0.33 0.19 4.83 0.318 8.07 0.010 0.254 0.020 0.508 0.030 0.762 MAX 0.213 5.41 0.213 5.41 0.074 1.88 0.010 0.390 0.84 2.13
E
032697 11/11

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